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Hu Xu

3D-GCP

A closed-form expression of cdf for 3-D circuits with only WID critical paths is provided.

The expressions of cdf for D2D critical paths are not obtained, while the lower and upper bounds are provided.

SPICE and gate-level Monte Carlo simulations are used to provide benchmarks.

Posted by Hu Xu at 17:33
Impact of D2D and WID fluctuations on FMAX distribution

WID primarily impacts the FMAX mean and D2D impacts the majority of FMAX variance

Impact of D2D & WID on the Critical Path Delay Distribution

fD2D-Tcp, nom = N (Tcp, nom, sigma2D2D-Tcp, nom)

fWID-Tcp, nom = N (Tcp, nom, sigma2WID-Tcp, nom)

Posted by Hu Xu at 15:56
CAD framework for memory and memory-logic 3-D systems

Challenge and Objective

  1. New models to accurately describe the power and speed benefits due to 3-D integration
  2. Novel design solutions (at different layers of abstraction) to address thermal, power delivery, synchronization, and SI across and within the planes of 3-D stack
  3. A holistic approach for DRAM or DRAM-logic 3-D system, which produces a CAD framework that embodies thermal, power and delay models
  4. The framework supports the exploration of design space based on manufacturing tech.,  packaging, # of planes, etc. 

Approach

  1. Cohesive integration of a broad spectrum of models
    • For TSV, analytic expressions or simulation of specific structures with electromagnetic simulators
    • For DRAM, first-order analytic expressions or/and models provided by vendors for latency and power consumption
    • For logic circuits, info. related to power consumption, power densities, and current demand can be extracted through high level simulations or provided by Intel Lab
  2. Evaluate different design trade-offs for a stack of 3-D DRAM/LOGIC system, investigating how best to construct these systems while minimally altering the individual components
  3. Placement of TSVs to satisfy bandwidth requirement and density constraints
  4. Design of a circuit that can dynamically adjust the storage in 3-D DRAM to balance power densities within 3-D stacks

Milestones

  1. Adapt and enhance the existing models for TSVs including thermal and electrical characteristics of the interconnects
  2. Model the behavior of the individual circuits of DRAM and processors
  3. Apply existing methodologies for the thermal modeling of a DRAM 3-D stack
  4. Integrate TSV density, power, and thermal modeling in a CAD framework

 

Posted by Hu Xu at 21:43
Paper for DATE

The paper for DATE2010 has been uploaded.

Now optimizing the Matlab code to speed up the computation.

500 trees cases (global) is now running. Intermediate have been finished.

Posted by Hu Xu at 15:23
Start the form

 start to fill the form of the candidacy exam.

Posted by Hu Xu at 15:13
Exam completed

The final exam was completed on 6.25. 

Posted by Hu Xu at 15:13
paper_v2

Paper_v2 is completed. 

Modify the proof of the effeciency of the iteration, and add some intro. to ISQED'09 paper to present their ignorance on the relation between the delays of different planes.

Posted by Hu Xu at 23:07
Feedback of 1st version for ICCAD
  1. Modify the grammar mistakes and typos;
  2. reduce the number of equations, especially for Elmore model;
  3. describe the case that no repeater is needed for a segment;
  4. modify the description for the Proof;
  5. emphasize the speciality of this work in Intro.;
Posted by Hu Xu at 20:12
modeling the "opamp" module

A simple module of the amplifier in VHDLAMS has been completed. 

The method to compile a vhdlams file is understood.

Posted by Hu Xu at 14:47
Draft for repeater insertion

The first version of the  paper "repeater insertion for 3-D interconnect" has been released. Something needs to complete:

  1. Introduction needs to be enriched, especially adding reference to the new 3-D buffer planning paper.
  2. Check the typo of the last two pages.
  3.  
Posted by Hu Xu at 14:43