Cette page appartient aux archives web de l'EPFL et n'est plus tenue à jour.
This page belongs to EPFL's web archive and is no longer updated.

Interconnect Analyzer Tool Project Blog

Week 25
Project Status:

- Finished the Report and handed it in. Phew!


Breaking News:

- The last phases of the hardware tests were a real triumph! A successful readout could be performed with ChipScope. It has been verified that the emulated frames were delivered correctly to the IAT, that the rule modules triggered correctly and at the right time, that the storage section inside the IAT gathered the right frames perfectly and finally that the frames at the readout did correspond with my predictions! The only point is that the emulating secquence activation still needs some slight modifications.


To be done in the future:

- Adapt the Emulator Activation Architecture, so that a relaunch of the frames becomes possible without recharging the programming file onto the chip.

- Generate the Emulator-Frames for the demo at the end. Cleverly choose the sequences to be tested and the corresponding rule modules.

- Begin to think about the presentation which will be held at September 26th (I am still not sure if it is the 27th).
Posted by Christof Bruetsch at 10:30
Week 24
Project Status:

- Generated two test-sequences with the aid of the Testframe-Generator. They simulate a read and a write transaction.
- Added a first version of a QuickStart Guide as a part of the appendix of the report.
- Added most of the written code in the appendix section of the report.
- Had to tinker on the IAT. The signals of main importance got pruned in the P&R phase. Now, with some additional code, it should work.

To be done in the future:

- Work hard on the conclusion & introduction sections, as they are crucial parts of the report.
- Adding an abstract for the IAT project.
- Opt.: Add some images to the QuickStart Guide.
- Opt.: Make the Appendixes more prettier.

-> AIM: FINISH THE REPORT THIS WEEK (deadline is tuesday, 6th September!)
Posted by Christof Bruetsch at 9:46
Week 23
Project Status:

- Finished a working ParityChecker. Now needs less resources - the whole design got a lot "lighter" with this modification. It is however based on a pipelined architecture. So the results always arrive with a certain delay. But as the interconnected rules have also a delay of at least two clock cycles, the inconvenience is negligible.
- Added some analysis (from synthesis) parts in the report.
- Removed a bug in the Frame Sequence Generator. Emulated idle bus behaviour was not recognized.

To be done in the future:

- Define transaction contents out of the PPC970FX manual and generate test-sequences for the demonstation. Begin with two working transactions.
- Modify the introduction of the report with better visual hints.
- Adding a Manual, some sort of QuickStart Guide for a future user of the IAT environment.
- Modify the appendix of the report.
- Adding an abstract for the IAT project.
Posted by Christof Bruetsch at 14:24
Week 22
Project Status:

- Made a major changement in the emulator: Generated a RAM core, replacing the FIFOs. Together with the emulator, the testframe generator has been adapted to generate the RAM entries instead of the XCSR write commands. However it still needs some modifications.
- Removed a major bug from the testframe generator.
- Completed the report (95%). Some parts still need to be revised or added.


To be done in the future:

- Still trying to modify the parity checker.
- Add the last remaining parts of the report. Make major revisions.
Posted by Christof Bruetsch at 9:42
Week 21
Project Status:
- First period of tests on the hardware have been successful after some minor changes in the ISLE file.
- Testbench sequences can now be generated from a sequence specification file.
- Parity Checker still not working, but a new solution is on the way.


Subsequent on-chip tests (on wednesday 27th, thursday, 28th):

- After several tries and analysis' via JTAG, we could deduct the error in the IAT_Isle that was responsible for blocking the system. Communication via the XCSR bus is now possible.


To be done in the next two weeks (CES supervisor's vacation):

- Trying to modify the parity checker. The bunch of XORs make the whole design overmap. So the new solution will consist of designing a unit, where just a few bits are compared and then gathered together with all the other paritychecked parts.
- Make a major changement in the emulator: Trying to take RAM instead of the FIFO architecture, which will allow us to perform a prestoring of the sequences that we want to test, disabling the need for the FIFO filling via XCSR.
- Update the report and try to complete it to 95%.
Posted by Christof Bruetsch at 12:45
Week 20
Project Status:

- Added Xilinx generated cores for the storage section. As we have enough Block RAM at our disposal, a better area occupation can be achieved.
- Found that the storage section was not primarily the cause for the overmapping. It was the parity checker module. I have removed this module in a first time so that at least the place&route works fine.
- The generator/parser generates now code that is adapted to the new architecture.

First on-chip test (on friday, 22th):

- The IAT_Isle got blocked, most probably because the XCSR protocol was not well defined, i.e. not every possible case has been taken into account.


To be done this week:

- Try to come up with a better version of the parity checker. Possible would be a "more-than-one-single-cycle" checker
- Correct the IAT_Isle in the XCSR protocol FSM section so that the following tests will be successful.
- Create some sort of testbench sequence generator for the emulation of some typical emulated transactions (different READs, WRITEs) with and without errors.
Posted by Christof Bruetsch at 14:20
Week 19
Project Status:

- Added the necessary attributes to guarantee an errorfree and sense-making synthesis.
- The ISLE simulates nicely.
- The hardware section has been completed and made ready for P&R. At the meeting, we tried to make it work, however at the mapping stage we always got an "overmapped" error. So there has to be a bug somewhere. It generated lots of slices, where the cause lies most probably in the selfdefined storage section.


To be done this week:

- Remove the existing storage section and replace it with cores generated by the Xilinx Core Generator; take the same principle as we used for the emulator FIFOs.
- If this does not help, search for another component that makes the program overmap the chip.
- Update the generator/parser. The flexible storage generation has to be adapted to the new environment with the cores.
Posted by Christof Bruetsch at 18:07
Week 18
Project Status:

- Finished the Emulator-IAT interface. The latter now accepts the signal-format delivered by the emulator section.
- Created a first version of the ISLE. Embedded the necessary modules: the XCSR central and an XCSR slave module. Through this architecture, we will be able to feedf the emulator with data.
- Enhanced the RDL (and hence the grammar) to be able to distinguish between IN and OUT rules, i.e. to prevent false detections when a rule checker is applied on both IN and OUT buses.
- Furthermore, a clearly defined scope of the RDL has been established. This enables us to get to know, what the limitations of the description language are, i.e. what can be described and what is not covered.


To be done this week and in the near future:

- The ISLE has to be modified. The unused signal lines must not be removed, otherwise the ISLE will not fit into the design.
- When finished with the ISLE, begin with the simulations. Always make synthesis runs in parallel to track down errors more efficiently.
- Do not forget to go on with the report...
Posted by Christof Bruetsch at 9:36
Week 17
Project Status:

- Analyzed the feedback from the presentation (content and performance comments)
- Adapted the grammar / scanner / parser / generator to the ability to define functional modules. The first example of a functional unit is the parity checker that has been added as VHDL source. If needed, a special keyword in the grammar will stand for the integration of the desired functional unit during code generation.


To be done this week and in the near future:

- Add the neccessary pieces in the grammar in order to guarantee a minimal required set of possible instructions for the rule checking.
- Define clearly the limits of the grammar and the whole description language. What will be inplemented and what will not be covered.
- Modify the emulator - IAT interface. The signal gathering module has to be adapted to the new frame formats.
- Create the link between the emulator and the XCSR interface.
- Try to create an isle representation file out of all these components.
Posted by Christof Bruetsch at 9:59
Week 16
Project Status:

- Analysis of PSL (accellera) completed.
- Additional read-out control module for the gathering of internal IAT signals has been created. It will be active after several successful sequences of observation.
- Created a preliminary version of the emulator. It consists of a FIFO section that stands as a storage vault for the IN and OUT of the Elastic I/O. Furthermore it contains a controller that regulates start and stop of the IAT as well as for the emulator itself. The section has already been simulated successfully. However, the interface with the XCSR components has not yet implemented.


Important news:

- The intermediate presentation will take place at Monday, June 27th, 11:00h, in the room INF113


To be done this week:

- Work on the presentation (highest priority).
- Evaluate the feedbacks after the presentation.
- Modify the emulator - IAT interface. The signal gathering module has to be adapted to the new frame formats (low priority).
- Create the link between the emulator and the XCSR interface (low priority).
Posted by Christof Bruetsch at 9:35
Page : 1 2 3 Next »