We are happy to announce that on January 25th, 2019 Andrea Bonetti has successcully completed and defended his PhD thesis with the title: "Low-Power Design of Digital VLSI Circuits around the Point of First Failure". We congratulate him for this significant achievement.
New book, edited by M. Coustas and C. Dehollaine on "Power Managemen for Internet of Everything" with a contribution from our lab on "Challenges and Approaches to Variation-Aware Low Power VLSI Design"
The Swiss Research Magazine "HORIZONS" published an article on our latest Polar Decoder Chip for 5G Wireless Communication using 28nm FDSOI technology.
Potential future EPFL EE students having fun some of the Arcade-Game projects of the 2017 hands-on class in "Digital System Design" at the "Journée des Gymnasiens" of EPFL.
We are happy to announce that on June 9th 2017 Hazar Yüksel has successcully completed and defended his PhD thesis (conducted at and in collaboration with IBM Zürich) with the title: "High-Speed Wireline Link Design". We congratulate him for this significant achievement.
This demo was shown at MobiHoc 2015: https://youtu.be/ENnFAYJsDXo